1. Field of the Invention
The present invention relates in general to a programmable phase shifter for phase shifting a periodic input signals by an adjustable amount, and in particular to a self-calibrating programmable phase shifter.
2. Description of Related Art
FIG. 1 illustrates a prior art programmable phase shifter 10 for phase shifting a periodic input signal T.sub.0 by an adjustable phase angle to produce an output signal T.sub.OUT. The phase angle is controlled by, for example, 10-bit input control data N. Ideally phase shifter 10 should provide a phase shift between T.sub.0 and T.sub.OUT of (N/N.sub.MAX))P.sub.0 where P.sub.0 is the period of the T.sub.0 signal and N.sub.MAX is the maximum value of N. Since N is a 10-bit number, N.sub.MAX may be as large as 210-1. However the actual phase shift shifter 10 provides will deviate from the ideal linear function of N.
Phase shifter 10 includes a tapped delay line 12 formed by a set of differential or single-ended buffers 14 connected in series for successively delaying the T0 signal to produce a set of L "tap" signals TAP.sub.1 -TAP.sub.L at the buffer outputs. L may be any value larger than 1 and is determined by the number of buffers forming delay line 12. In the example illustrated in FIG. 1, L is 32. Each successive tap signal TAP.sub.1 -TAP.sub.32 is delayed from its preceding tap signal by the inherent delay of an buffer 14. The T.sub.0 and TAP.sub.32 signals are applied as inputs to a conventional delay lock loop (DLL) controller 16 that provides a BIAS signal to each buffer 14. The BIAS signal controls the inherent delay of each buffer 14. DLL controller 16 adjusts the BIAS signal so that the TAP.sub.32 signal is phase locked to the T.sub.0 signal. Thus the total delay between T.sub.0 and TAP.sub.32 is equal to the period P.sub.0 of T.sub.0. When all buffers 14 are similar, each buffer's delay is close to the average buffer delay of P.sub.0 /32. However there will be some variation in buffer delay due to process or environmental differences between the buffers.
The tap signals TAP.sub.1 -TAP.sub.32 provide inputs to a multiplexer 18 controlled by the upper five bits NH of 10-bit input control data N. Multiplexer 18 selects one of its input signals TAP.sub.1 -TAP.sub.32 and provides it as an input signal T.sub.S to a programmable delay circuit 20. Delay circuit 20 delays the T.sub.S signal by from 0 to 31 "unit delays" where a unit delay is P.sub.0 /(L*N.sub.MAX). The amount of the delay provided by delay circuit 20 is selected by the lower five bits NL of control data N. Thus the 10-bit input control data N controls the phase shift between T.sub.0 and T.sub.OUT with a nominal resolution of P.sub.0 /2.sup.10.
While the resolution of phase shifter 10 is nominally P.sub.0 /N.sub.MAX, various factors affect the accuracy of the phase shift that it provides. Deviation in inherent delay of any buffer 14 from P.sub.0 /32 and any error in the delay provided by programmable delay circuit 20 will render the phase shift between T.sub.0 and T.sub.OUT a non-linear function of N. Also the inherent signal path delay through multiplexer 18 will introduce an offset into the phase shift between T.sub.0 and T.sub.OUT. When the various delays provided by programmable delay circuit 20 are adjustable, phase shifter 10 can be calibrated by monitoring the phase shift between T.sub.0 and T.sub.OUT and adjusting the delay provided by programmable delay circuit 20 for each value of NL. However such a manual calibration process is tedious and time consuming.
What is needed is a phase shifter that provides a linear relationship between the phase shift it provides and the value of its input control data and that can be quickly and accurately calibrated.